Design verification is essential to virtually any very large scale integration (VLSI) design project. One of the popular verification methods is logic simulation. Logic simulation software reports on how a circuit under design responds to a sequence of input vectors, so the designer can judge whether the circuit behaves as expected over an input sequence. The more vectors simulated, the greater confidence the designer has in the correctness of the designing circuit.
As circuit complexity increases and the time to market shortens, inadequate simulation speed becomes a major bottleneck in the design process. As a result, several special purpose machines have been built to simulate/emulate complex logic designs in hardware, rather than software. Such emulation/acceleration devices can provide several orders of magnitude of speed improvement during the simulation/emulation process. Thus, the necessity and usefulness of such devices has increased enormously with growth in the complexity of integrated circuits.
An emulation/acceleration engine operates to mimic the logical design of a set of one or more integrated circuit chips. The emulation of these chips in terms of their logical design is highly desirable for several reasons which are discussed in more detail below. It is, however, noted that the utilization of emulation/acceleration engines has also grown up with and around the corresponding utilization of design automation tools for the construction and design of integrated circuit chip devices. In particular, as part of the input for the design automation process, logic descriptions of the desired circuit chip functions are provided. The existence of such software tools for processing these descriptions in the design process is well mated to the utilization of emulation/acceleration engines which are electrically configured to duplicate the same logic function that is provided in a design automation tool.
Utilization of emulation/acceleration devices permits testing and verification, via actual electrical circuits, of logical designs before these designs are committed to a so-called “silicon foundry” for manufacture. The input to such foundries is the functional logic description required for the chip, and its output is initially a set of photolithographic masks which are then used in the manufacture of the desired electrical circuit chip devices. However, it is noted that the construction of such masks and the initial production of circuit chips is expensive. Any passage of a given device having the prescribed logic functionality though such a foundry is an expensive and time consuming process which clearly should be undertaken only once. It is the purpose of emulation/acceleration engines to ensure such a single passage from the functional logic design stage through the stage of chip production via such a foundry.
Verifying that logic designs are correct before committing a design to manufacturing, therefore, eliminates the need for costly and time-consuming multiple passes through a silicon foundry. Debugging logic errors deep inside a logic chip can be extremely difficult because of very limited observability. Emulation provides two very significant advantages. Firstly, the proper verification of a functional logic design eliminates the need for a second costly passage through the foundry, and, secondly, and just as importantly, getting the design “right the first time” means that the design does not have to be corrected in the foundry. Accordingly, production delays are significantly reduced and the time to market for the particular technology/technology improvements embedded in the integrated circuit chip is greatly reduced, thus positively impacting the ability to deliver the most sophisticated technological solutions to consumers in as short of time as possible.
An additional advantage that emulation/acceleration systems have is that they act as a functioning system of electrical circuits which makes possible the early validation of software which is meant to operate the system that the emulator/accelerator is mimicking. Thus, software can be designed, evaluated and tested well before the time when the system is embodied in actual circuit chips. Additionally, emulation/acceleration systems can also operate as simulator-accelerator devices thus providing a high speed simulation platform.
FIG. 1A illustrates a high-level block diagram of a typical emulation/acceleration system 10 (hereinafter referred to as emulation system 10), which is controlled by a host workstation 12. Emulation system 10 includes at least one emulation board 14, which, in turn, contains a plurality of emulation modules 16, as shown in FIG. 1B. Each emulation module 16 contains a plurality of emulation processors 18, as shown in FIG. 1C. Each emulation processor 18 is programmed to evaluate a particular logic function (for example, AND, OR, XOR, NOT, NOR, NAND, etc.). The programmed emulation processors 18, together as a connected unit, emulate an entire desired logic design under test 11 (i.e., the programmed emulation processors form part of a simulation “model” 15 for the logic design). This simulation model 15 may also include some additional controllability/observability logic to aid in the simulation/emulation process.
The overall simulation throughput of such a system is controlled by the interface between the simulation model 15 running on the emulation system 10 and a runtime control program 20 running on a host workstation 12. Control program 20 interfaces with emulation board 14 via a control card 27. Control card 27 is further coupled to emulation board 14 via connector 19. Transactions between runtime control program 20 and the emulation board 14 include reading and writing the values of logic facilities contained within the simulation model and the execution of cycles to recalculate the model state by toggling the value of clock signals that propagate to latch facilities within simulation model 15.
Emulation system 10 typically contains logical designs having memory elements (e.g., arrays) of various sizes and dimensions. Emulation system 10 has a finite amount of physical memory resources where the logical arrays can reside during simulation. This physical memory is comprised of fixed-size components such as SRAM and SDRAM. One of the responsibilities of the software that compiles logical models for the emulator is to map (i.e., place or assign) the logical arrays within the logical design into the physical memory.
The physical memory resources of the emulation system 10 can be a limiting factor in the success of building a logic model, depending on the efficiency of mapping the logical arrays to the physical memories. Inefficiencies occur when the width of the logical array is not an even multiple of the width of the physical memory. As an example, if the width of the physical memory is 64 bits and the width of the logical array is only 24 bits, then there are 40 physical bits unused for every row in the logical array. Similar conditions occur when the logical array is wider than the physical memory. A 72-bit wide logical array will use up the entire width of the first 64-bit wide physical memory, but only use 8 of the 64 bits in a second physical memory. This represents a waste of 56 bits for every logical row. The greatest waste occurs when logical arrays are very narrow compared to the width of the physical memories. The general trend in memory technologies is to support new computing systems with ever widening data busses.
FIG. 2 shows a prior art method of partitioning and placing a logical array into multiple physical memories. If the width of an original logical array 42 is half the width of a physical memory 45, half of the physical memory is wasted or unused, as shown at shaded area 46.
There is a need for a method, apparatus and computer product to efficiently utilize previously inaccessible memory in an emulation system. Such a feature would enable models with large and diverse memory requirements to be successfully compiled that would have previously failed due to insufficient accessible physical memory.